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Ordering number : ENN*7023
CMOS IC
LC74982W
LCD TV Scan Converter IC
Preliminary Overview
The LC74982W is an LCD display scan converter IC that converts NTSC and PAL TV signals to XGA resolution. The video signal-processing circuits required to implement an LCD TV set can be easily formed by combining this IC with a digital decoder, a microcontroller, and an LCD panel. Since this IC does not require an external frame memory for resolution conversion, it can contribute to minimizing total costs. As additional functionality, it also provides inputs for personal computer video (up to XGA) and digital TV (480p/480i). Since LC74982W operation is based on expansion (resolution increasing) processing, depending on the input resolution, it can also support use of, for example, 800 x 600 and 800 x 480 dot resolution LCD panels. Thus the LC74982W can be used in a wide range of applications. * Built-in correction (LUT technique. Each 8-bit R, G, and B signal is independently programmable.) * Built-in OSD function (8 colors, 253 characters) * I2C bus interface * Constant frame-rate processing (identical frame periods in the input and output signals) adopted so that no external memory is required.
Specifications
* Supply voltage: 3.3 V (input pins are 5 V tolerant) * Maximum operating frequency: 65.0 MHz * Package: SQFP208
Applications
* LCD TVs, monitors, and projectors * PDP displays * Car television and car video monitors
Features
* NTSC and PAL input support: 24-bit or 16-bit digital YCbCr signal input * PC input support: Personal computer 24-bit digital RGB signal input at resolutions up to XGA * DTV (480i / 480p) input: 24-bit or 16-bit digital YCbCr input * Two-phase progressive scan RGB 18-bit (24 bit) and 36bit (48 bit) signal output * Simulated increased color-depth processing at 6-bit mode. Values in parentheses apply in 8-bit mode. * YCbCr to RGB conversion * Interlaced to progressive scan conversion * Resolution conversion (enlargement) * Variable display size and display position (independently settable in the horizontal and vertical directions) * Image quality adjustments: brightness, contrast, color, sharpness, color phase, black balance, and white balance
Package Dimensions
unit: mm 3210-SQFP208
[LC74982W]
30.6 0.5 28.0
156 157
105 104
208 1
(0.5) (1.25) 0.2
53 52
(3.2) 0.15
0.35
3.8max
28.0
SANYO: SQFP208
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
91801TN (OT) No. 7023-1/14
30.6
LC74982W
I/O Specifications
Input Signal Overview
Signal type Pin No. 6 to 13 54 to 61 Video signals 16 to 23 64 to 71 26 to 33 74 to 81 90 91 Sync signals 92 93 94 95 96 Data enable signals 97 36 Pixel clocks 39 42 167 BLKIV CLKITV CLKIDTV CLKIPC XTAL Vertical enable NTSC/PAL clock DTV clock PC clock Display clock * Fixed frequency crystal oscillator (65 MHz maximum) * Three independent input systems Pin YIN7 to 0 RIN7 to 0 UIN7 to 0 GIN7 to 0 VIN7 to 0 BIN7 to 0 HITV VITV HIDTV VIDTV HIPC VIPC BLKIH Y/Y/R Description Notes * NTSC, PAL, and DTV (480i and 480p) inputs YCbCr signals conform to the CCIR 601 standard. The YC C signal is a multiplexed CbCr signal (4:2:2). * PC input (up to XGA)
C/Cb/G
-/Cr/B NTSC/PAL horizontal sync signal NTSC/PAL vertical sync signal DTV horizontal sync signal DTV vertical sync signal PC horizontal sync signal PC vertical sync signal Horizontal enable
* Three independent systems for both horizontal and vertical sync signals * Any input polarity may be used. Internal automatic-discrimination.
* Input with the same logic. The polarity can be inverted internally. * A composite video signal can be input to BLKIH. (BLKIV must be tied high in this case.)
Output Signal Overview
Signal type Pin No. 106 to 111 114 to 119 Video signals in 6-bit output mode 122 to 127 130 to 135 138 to 143 146 to 151 106 to 111, 114, 115 116 to 119, 122 to 125 Video signals in 8-bit output mode 126, 127, 130 to 135 138 to 143, 146, 147 182 to 189 192 to 199 Sync signals 162 163 102 103 154 Pixel clocks 155 158 159 Pin ROEVEN5 to 0 GOEVEN5 to 0 BOEVEN5 to 0 ROODD5 to 0 GOODD5 to 0 BOODD5 to 0 ROEVEN7 to 0 Description Even pixels, red Even pixels, green Even pixels, blue Odd pixels, red Odd pixels, green Odd pixels, blue Even pixels, red * Each of the RGB channels is an 6-bit 2-phase signal. * The output mode can be switched to single-phase output mode. (Output from the ODD pin) Notes
GOEVEN7 to 0
Even pixels, green
* Each of the RGB channels is an 8-bit 2-phase signal. * The output mode can be switched to single-phase output mode. (Output from the ODD pin)
BOEVEN7 to 0
Even pixels, blue
ROODD7 to 0 GOODD7 to 0 BOODD7 to 0 HOUT VOUT BLKHOUT BLKVOUT DCLK1 DCLK1B DCLK2 DCLK2B
Odd pixels, red Odd pixels, green Odd pixels, blue Horizontal sync signal Vertical sync signal Horizontal enable Vertical enable Single-phase clock Single-phase clock (inverted) Two-phase clock Two-phase clock (inverted)
* The sync period, position, and polarity can be set. * A composite sync signal can be output from VOUT. * The enable period and the polarity can be set. * A composite signal can be output from BLKVOUT. * Outputs the same frequency as that of the crystal oscillator. * Outputs a frequency 1/2 that of the crystal oscillator.
Data enable signals
No. 7023-2/14
LC74982W Control Signal Overview
Signal type Pin No. 172 Three-wire bus 173 174 175 I2C-bus 176 Pin AICS AIDA AICK SDA SCL Chip select Data bus Bus clock Data bus Bus clock * Used to set the internal control registers and to output internal status information. * The slave address is "0111000+ (R/W)". Description Notes * Used for OSD control and correction characteristics settings.
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Storage temperature Operating temperature Symbol VDD max VI VO Pd max Tstg Topr Ta = 70C Conditions Ratings -0.3 to +4.6 -0.5 to + 5.5 -0.3 to VDD + 0.3 0.9 -55 to +125 -30 to +70 Unit V V V W C C
Note: While the standard operating temperature is -30 to +70C, for applications such as automotive applications, it can also be used over the range -40 to +85C. Note, however, that the value of the allowable power dissipation differs somewhat between these two cases. Contact your SANYO representative for details if you need to use this device with the latter (wider) operating temperature range.
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 3.0 0 typ 3.3 -- max 3.6 5.5 Unit V V
I/O Pin Capacitances at Ta = 25C, VDD = VI = 0 V
Parameter Input pins Output pins Bidirectional pins Symbol CIN COUT CI/O f = 1 MHz f = 1 MHz f = 1 MHz Conditions Ratings min -- -- -- typ -- -- -- max 10 10 10 Unit pF pF pF
DC Characteristics at Ta = -30 to +70C, VDD = 3.0 to 3.6 V
Parameter Symbol CMOS level CMOS level Schmitt CMOS level CMOS level Schmitt VI = VDD VI = VDD, with pull-down resistors attached. VI = VSS Type B4, IOH = -2 mA Output high-level voltage VOH Type B8, IOH = -4 mA Type B12, IOH = -6 mA Type B4, IOL = 2 mA Output low-level voltage VOL IOZ RDN IDD Outputs open, VI = VSS or VDD Type B8, IOL = 4 mA Type B12, IOL = 6 mA Output leakage current Pull-down resistance Quiescent current* In the high-impedance output state Conditions Ratings min 0.7 VDD 0.75 VDD -- -- -10 10 -10 VDD - 0.8 VDD - 0.8 VDD - 0.8 -- -- -- -10 35 -- typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70 -- max -- -- 0.2 VDD 0.15 VDD +10 100 +10 -- -- -- 0.4 0.4 0.4 +10 140 100 Unit V V V V A A A V V V V V V A k A
Input high-level voltage
VIH VIL IIH IIL
Input low-level voltage
Input high-level current Input low-level current
Note: * Certain of the input pins include built-in pull-down resistors. The quiescent current drain cannot be guaranteed in certain situations due to the structure of these circuits.
No. 7023-3/14
LC74982W Pin Assignment
156
DVSS DCLK2 DCLK2B DVDD DVSS HOUT VOUT VIRST DVDD DVSS XTAL DVDD DVSS EXCTR MUTE AICS AIDA AICK SDA SCL PDOWN1 PDOWN2 CLKIO DVDD DVSS TSTOA7 (GOODD0) TSTOA6 (GOODD1) TSTOA5 (GOODD2) TSTOA4 (GOODD3) TSTOA3 (GOODD4) TSTOA2 (GOODD5) TSTOA1 (GOODD6) TSTOA0 (GOODD7) DVDD DVSS TSTOB7 (BOODD0) TSTOB6 (BOODD1) TSTOB5 (BOODD2) TSTOB4 (BOODD3) TSTOB3 (BOODD4) TSTOB2 (BOODD5) TSTOB1 (BOODD6) TSTOB0 (BOODD7) TSTMOD3 TSTMOD2 TSTMOD1 TSTMOD0 TSTSUB3 TSTSUB2 TSTSUB1 TSTSUB0 DVDD 208
157
DVDD DCLK1B DCLK1 DVSS DVDD BOODD5 (TEST3) BOODD4 (TEST2) BOODD3 (TEST1) BOODD2 (TEST0) BOODD1 (ROODD7) BOODD0 (ROODD6) DVSS DVDD GOODD5 (ROODD5) GOODD4 (ROODD4) GOODD3 (ROODD3) GOODD2 (ROODD2) GOODD1 (ROODD1) GOODD0 (ROODD0) DVSS DVDD ROODD5 (BOEVEN7) ROODD4 (BOEVEN6) ROODD3 (BOEVEN5) ROODD2 (BOEVEN4) ROODD1 (BOEVEN3) ROODD0 (BOEVEN2) DVSS DVDD BOEVEN5 (BOEVEN1) BOEVEN4 (BOEVEN0) BOEVEN3 (BOEVEN7) BOEVEN2 (BOEVEN6) BOEVEN1 (BOEVEN5) BOEVEN0 (BOEVEN4) DVSS DVDD GOEVEN5 (GOEVEN3) GOEVEN4 (GOEVEN2) GOEVEN3 (GOEVEN1) GOEVEN2 (GOEVEN0) GOEVEN1 (ROEVEN7) GOEVEN0 (ROEVEN6) DVSS DVDD ROEVEN5 ROEVEN4 ROEVEN3 ROEVEN2 ROEVEN1 ROEVEN0 DVSS
105
155 160
150
145
140
135
130
125
120
115
110
105 100
165 95
170 90
175 85
180
LC74982W (Top view)
80
185 75
190 70
195 65
200 60
205 5 10 15 20 25 30 35 40 45 55 50
104 DVDD BLKVOUT BLKHOUT RST DVSS DVDD PLLH BLKIV BLKIH VIPC HIPC VIDTV HIDTV VITV HITV DVSS DVDD CLPCR CLPCB CLPY CLPP DVSS DVDD BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 DVSS DVDD GIN0 GIN1 GIN2 GIN3 GIN4 GIN5 GIN6 GIN7 DVSS DVDD RIN0 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 RIN7 DVSS 53
1
* ( ): Values in parentheses apply in 8-bit mode.
DVSS OSDRIN OSDGIN OSDBIN OSDEN YIN7 YIN6 YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 DVDD DVSS UIN7 UIN6 UIN5 UIN4 UIN3 UIN2 UIN1 UIN0 DVDD DVSS VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 DVDD DVSS CLKITV DVDD DVSS CLKIDTV DVDD DVSS CLKIPC DVDD SCANMOD SCANEN AVSS PDO AVDD AVSS VCOCNT VOCORNG AVDD
52
No. 7023-4/14
LC74982W Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin DVSS OSDRIN OSDGIN OSDBIN OSDEN YIN7 YIN6 YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 DVDD DVSS UIN7 UIN6 UIN5 UIN4 UIN3 UIN2 UIN1 UIN0 DVDD DVSS VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 DVDD DVSS CLKITV DVDD DVSS CLKIDTV DVDD DVSS CLKIPC DVDD SCANMOD SCANEN AVSS PDO AVDD AVSS VCOCNT VCORNG AVDD I/O type I/O P I I I I I I I I I I I I P P I I I I I I I I P P I I I I I I I I P P I P P I P P I P I I P O P P I I P g74100m06 g74100m06 zwp3vpll3 g74980m03 g74980m03 g74980m05 g74980m05 g74980m05 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 Power supply GND Digital decoder Power supply GND PLL Power supply GND Digital interface Power supply Open Open GND Loop filter Power supply GND Loop filter Resistor Power supply LSB Digital system power supply: 3.3 V Digital system ground TV clock input (data rate) Digital system power supply: 3.3 V Digital system ground DTV clock input Digital system power supply: 3.3 V Digital system ground PC clock input (data rate) Digital system power supply: 3.3 V Scan test mode Scan test enable Analog system ground Charge pump output (open) Analog system power supply: 3.3 V Analog system ground VCO control input (Connect to AVSS.) VCO bias resistor input (Connect to AVSS.) Analog system power supply: 3.3 V g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 Power supply GND Digital decoder or ADC or Digital Interface LSB Digital system power supply: 3.3 V Digital system ground MSB Cr signal input or B signal input g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 Power supply GND Digital decoder or ADC or Digital Interface LSB Digital system power supply: 3.3 V Digital system ground MSB C (CbCr multiplexed) signal input or Cb signal input or G signal input Type Connection GND Caption OSD microcontroller Caption OSD microcontroller Caption OSD microcontroller Caption OSD microcontroller Digital decoder or ADC or Digital Interface Digital system ground OSD red input (NTSC only) OSD green input (NTSC only) OSD blue input (NTSC only) OSD data enable (NTSC only) MSB Y signal input or R signal input Notes
Continued on next page.
No. 7023-5/14
LC74982W
Continued from preceding page.
Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Pin DVSS RIN7 RIN6 RIN5 RIN4 RIN3 RIN2 RIN1 RIN0 DVDD DVSS GIN7 GIN6 GIN5 GIN4 GIN3 GIN2 GIN1 GIN0 DVDD DVSS BIN7 BIN6 BIN5 BIN4 BIN3 BIN2 BIN1 BIN0 DVDD DVSS CLPP CLPY CLPCB CLPCR DVDD DVSS HITV VITV HIDTV VIDTV HIPC VIPC BLKIH BLKIV PLLH DVDD DVSS RST BLKHOUT BLKVOUT DVDD I/O type I/O P I I I I I I I I P P I I I I I I I I P P I I I I I I I I P P O O O O P P I I I I I I I I O P P I O O P g74980m01 POB8 POB8 g74980m04 g74980m04 g74980m04 g74980m04 g74980m04 g74980m04 g74980m02 g74980m02 POB4 POB4 POT4 POT4 POT4 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 Power supply GND ADC ADC ADC ADC Power supply GND TV decoder TV decoder Digital interface Digital interface Digital interface Digital interface Digital interface Digital interface PLL Power supply GND Initialization circuit LCD module LCD module Power supply LSB Digital system power supply: 3.3 V Digital system ground Clamp pulse Y clamp level Cb clamp level Cr clamp level Digital system power supply: 3.3 V Digital system ground TV horizontal synchronizing signal input TV vertical synchronizing signal input DTV horizontal synchronizing signal input DTV vertical synchronizing signal input PC horizontal sync signal input PC vertical sync signal input Horizontal blanking signal input (composite blanking signal) Vertical blanking signal input (Held high in composite mode) PLL internal divider output Digital system power supply: 3.3 V Digital system ground System reset (reset to low) Horizontal data enable Vertical data enable or composite data enable Digital system power supply: 3.3 V g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 Power supply GND Digital Decoder or ADC or Digital Interface LSB Digital system power supply: 3.3 V Digital system ground MSB Cr signal input or B signal input g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 Power supply GND Digital Decoder or ADC or Digital Interface LSB Digital system power supply: 3.3 V Digital system ground MSB C (CbCr multiplexed) signal input or Cb signal input or G signal input Type Connection GND Digital Decoder or ADC or Digital Interface Digital system ground MSB Y signal input or R signal input Notes
Continued on next page.
No. 7023-6/14
LC74982W
Continued from preceding page.
Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin DVSS ROEVEN0 ROEVEN1 ROEVEN2 ROEVEN3 ROEVEN4 ROEVEN5 DVDD DVSS GOEVEN0 (ROEVEN6) GOEVEN1 (ROEVEN7) GOEVEN2 (GOEVEN0) GOEVEN3 (GOEVEN1) GOEVEN4 (GOEVEN2) GOEVEN5 (GOEVEN3) DVDD DVSS BOEVEN0 (GOEVEN4) BOEVEN1 (GOEVEN5) BOEVEN2 (GOEVEN6) BOEVEN3 (GOEVEN7) BOEVEN4 (BOEVEN0) BOEVEN5 (BOEVEN1) DVDD DVSS ROODD0 (BOEVEN2) ROODD1 (BOEVEN3) ROODD2 (BOEVEN4) ROODD3 (BOEVEN5) ROODD4 (BOEVEN6) ROODD5 (BOEVEN7) DVDD DVSS GOODD0 (ROODD0) GOODD1 (ROODD1) GOODD2 (ROODD2) GOODD3 (ROODD3) GOODD4 (ROODD4) GOODD5 (ROODD5) DVDD DVSS BOODD0 (ROODD6) BOODD1 (ROODD7) BOODD2 (TEST0) BOODD3 (TEST1) BOODD4 (TEST2) BOODD5 (TEST3) DVDD DVSS DCLK1 DCLK1B DVDD I/O type I/O P O O O O O O P P O O O O O O P P O O O O O O P P O O O O O O P P O O O O O O P P O O O O O O P P O O P POB12 POB12 POB4 POB4 POB4 POB4 POB4 POB4 Power supply GND LCD module LCD module Power supply MSB Digital system power supply: 3.3 V Digital system ground Data clock 1 (for single-phase data output) Inverted data clock 1 (for single-phase data output) Digital system power supply: 3.3 V (OPEN) POB4 POB4 POB4 POB4 POB4 POB4 Power supply GND LCD module MSB Digital system power supply: 3.3 V Digital system ground LSB Blue signal output (odd) or Blue signal single-phase output (Test output (Outputs a fixed low level.)) (MSB) POB4 POB4 POB4 POB4 POB4 POB4 Power supply GND LCD module MSB Digital system power supply: 3.3 V Digital system ground LSB Green signal output (odd) or Green signal single-phase output (Red signal output (odd) or Red signal single-phase output) (LSB) (MSB) POB4 POB4 POB4 POB4 POB4 POB4 Power supply GND LCD module MSB Digital system power supply: 3.3 V Digital system ground LSB Red signal output (odd) or Red signal single-phase output (B signal output (even)) POB4 POB4 POB4 POB4 POB4 POB4 Power supply GND LCD module MSB Digital system power supply: 3.3 V Digital system ground LSB Blue signal output (even) (MSB) (LSB) (Green signal output (even)) Green signal output (even) POB4 POB4 POB4 POB4 POB4 POB4 Power supply GND LCD module MSB Digital system power supply: 3.3 V Digital system ground LSB (MSB) (LSB) (Red signal output (even)) Type Connection GND LCD module Digital system ground LSB Red signal output (even) (LSB) Notes
Continued on next page.
No. 7023-7/14
LC74982W
Continued from preceding page.
Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin DVSS DCLK2 DCLK2B DVDD DVSS HOUT VOUT VIRST DVDD DVSS XTAL DVDD DVSS EXCTR MUTE AICS AIDA AICK SDA SCL PDOWN1 PDOWN2 CLKI0 DVDD DVSS TSTOA7 (GOODD0) TSTOA6 (GOODD1) TSTOA5 (GOODD2) TSTOA4 (GOODD3) TSTOA3 (GOODD4) TSTOA2 (GOODD5) TSTOA1 (GOODD6) TSTOA0 (GOODD7) DVDD DVSS TSTOB7 (BOODD0) TSTOB6 (BOODD1) TSTOB5 (BOODD2) TSTOB4 (BOODD3) TSTOB3 (BOODD4) TSTOB2 (BOODD5) TSTOB1 (BOODD6) TSTOB0 (BOODD7) TSTMOD3 TSTMOD2 TSTMOD1 TSTMOD0 TSTSUB3 TSTSUB2 TSTSUB1 TSTSUB0 DVDD I/O type I/O P O O P P O O O P P I P P O I I I I B I I I O P P O O O O O O O O P P O O O O O O O O I I I I I I I I P POB4 POB4 POB4 POB4 POB4 POB4 POB4 POB4 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 g74980m03 Power supply Digital system power supply: 3.3 V OPEN Test sub-mode (Must be left open in normal operation.) OPEN LSB (MSB) (LCD module) POB4 POB4 POB4 POB4 POB4 POB4 POB4 POB4 Power supply GND OPEN LSB Digital system power supply: 3.3 V Digital system ground MSB Test outputs (LSB) (B signal output (odd) or B signal single-phase output) (MSB) (LCD module) POB4 g74980m02 g74980m02 g74980m02 g74980m02 g74980m06 g74980m02 g74980m01 g74980m01 POB12 g74980m01 POB8 POB8 POB4 POB12 POB12 Type Connection GND -- -- Power supply GND LCD module LCD module -- Power supply GND VCO Power supply GND -- Microcontroller Microcontroller Microcontroller Microcontroller Microcontroller Microcontroller -- -- -- Power supply GND OPEN Digital system ground Data clock 2 (for two-phase data output) Inverted data clock 2 (for two-phase data output) Digital system power supply: 3.3 V Digital system ground Horizontal sync output Vertical synchronizing signal output or composite synchronizing signal output Crystal oscillator reset Digital system power supply: 3.3 V Digital system ground Crystal oscillator circuit output Digital system power supply: 3.3 V Digital system ground External control output (output controlled over the I2C bus) Mute control input (mute to low) 3-wire bus control chip select 3-wire bus control bus data 3-wire bus control bus clock I2C control data I2C control clock Must be tied high during normal operation. Must be tied high during normal operation. Input system clock output Digital system power supply: 3.3 V Digital system ground MSB Test outputs (LSB) (G signal output (odd) or G signal single-phase output) Notes
Test mode (Must be left open in normal operation.)
No. 7023-8/14
LC74982W Pin Type
I/O type RST g74980m01 PDOWN1 to 2 XTAL AICS, AIDA, AICK g74980m02 SCL BLKIH, BLKIV MUTE OSDRIN, OSDGIN, OSDBIN, OSDEN YIN0 to 7, UIN0 to 7, VIN0 to 7 g74980m03 SCANMOD, SCANEN RIN0 to 7, GIN0 to 7, BIN0 to 7 TSTMOD0 to 3, TSTSUB0 to 3 Leave open when unused.
A13543
Applicable pins
Function 3 to 5 V voltage handling input
Equivalent circuit
A13541
3 to 5 V voltage handling Schmitt input
A13542
3 to 5 V voltage handling pull-down input
HITV, VITV g74980m04 HIDTV, VIDTV HIPC, VIPC
3 to 5 V voltage handling pull-down Schmitt input
A13544
CLKITV g74980m05 CLKIDTV CLKIPC
3 to 5 V voltage handling OE input
A13545
CLPP, PLLH, POB4 ROEVEN0 to 5 (7), GOEVEN0 to 5 (7), BOEVEN0 to 5 (7), ROODD0 to 5 (7), GOODD0 to 5 (7), BOODD0 to 5 (7), VIRST, EXCTR, TST0A0 to 7, TST0B0 to 7, (TEST0 to 3) BLKHOUT, BLKVOUT HOUT, VOUT DCLK1, DBLK1B, DCLK2, DCLK2B CLKI0 4 mA drive output
POB8
8 mA drive output
A13546
POB12
12 mA drive output
POT4
CLPY, CLPCB, CLPCR
4 mA 3-state drive output
A13547
g74980m06
SDA
Open-drain I/O
A13548
g74100m06
VCOCNT, VCORNG
Analog through
zwp3vpll3
PDO
Charge pump output
A13549
Note: * All of the DVDD, DVSS, AVDD, and AVSS pins must be connected to the corresponding power or ground level. Do not leave any of these pins open.
No. 7023-9/14
IC Internal Block Diagram
When in 8-bit output mode
8 6 13 Y Y RGB Sharpness YCbCr R G B B G R Cb Cr G YCbCr Cr Color B R Color phase RGB Cb correction O S D 8 8
8 Input processing Expansion processing Output processing
6 or 8
YIN [7 : 0]
106 111 ROEVEN 106 115 114 119 GOEVEN 116 125 122 127 BOEVEN 126 135 130 135 ROODD 138 143 GOODD 146 151 BOODD 138 147 182 189 192 199
UIN [7 : 0] 16 23
VIN [7 : 0] 26 33
White balance Contrast Black balance Brightness
GIN [7 : 0] 54 61
Horizontal expansion
Color depth processing
Vertical expansion
BIN [7 : 0] 64 71
RIN [7 : 0] 74 81
HITV 92 94 91 93 95 96 97 Input clock generation circuit Three-wire bus control interface I2C bus control interface Input timing circuit
90 Output timing circuit
162 HOUT 163 VOUT 102 BLKHOUT 103 BLKVOUT
LC74982W
HIDTV
HIDPC
VITV
VIDTV
VIDPC
BLKIH
* Field discrimination * Horizontal sync signal polarity discrimination * Composite blanking signal discrimination and separation * Timing generation for all horizontal and vertical timings
* Input sync signal detection * Timing generation for all horizontal and vertical timings
BLKIV
Output clock generation circuit
36 CLKITV / CLKIDTV / CLKIPC
39
42
172
173
174
175
176 SDA / SCL
167
154
155
158
159 XTAL DCLK1 / DCLK1B / DCLK2 / DCLK2B
ILC05427
AICS / AIDA / AICK
No. 7023-10/14
LC74982W Sample Application Circuit (LCD TV/Monitor)
Y (8bit) Tuner Degital Decoder CbCr (8bit) Hsync Vsync VCR Pixel clocks
RO (6bit or 8bit)
LC74982W
GO (6bit or 8bit) BO (6bit or 8bit) RE (6bit or 8bit) GE (6bit or 8bit) BE (6bit or 8bit) BLK Hsync
TFT-LCD MODULE (XGA)
R (8bit) PC A/D G (8bit) B (8bit) Hsync Vsync PLL Pixel clocks
Vsync Pixel clocks
X'Tal 65.0MHz
Microcontroller LC86F3248A
No. 7023-11/14
LC74982W I/O Data Timing (1) Input data timing
tHI tCK
Input system clock tSU tHD tLO
VDD/2
Input data
VDD/2
Item Clock low-level period Clock high-level period Clock cycle Input data setup time
Pin CLKITV CLKIDTV CLKIPC YIN [7:0], UIN [7:0] VIN [7:0], RIN [7:0] GIN [7:0], BIN [7:0]
Parameter tLO tHI tCK tSU
min 7.5 7.5 15.0 0
max -- -- -- --
Unit ns ns ns ns
Input data hold time
HITV, VITV, HIDTV, VIDTV HIPC, VIPC, BLKIH, BLKIV
tHD
7.0
--
ns
Note: * We recommend using a duty of 50% for the input clock signal.
(2) Output data timing
tHI tCK
DCLK2B tLO tOUT
VDD/2
Output data
VDD/2
Item Clock low-level period Clock high-level period Clock cycle
Pin
Parameter tLO
min 15.0 15.0 30.0
max -- -- --
Unit ns ns ns
DCLK2, DCLK2B
tHI tCK
ROEVEN [5(7):0], GOEVEN [5(7):0] Output data delay time BOEVEN [5(7):0], ROODD [5(7):0] GOODD [5(7):0], BOODD [5(7):0] BLKHOUT, HOUT, VOUT tOUT 0 10 ns
No. 7023-12/14
LC74982W I/O Clock Timing (1) Input system clock timing
tHI CLKITV CLKIDTV CLKIPC tOUT tLO tCK
VDD/2
CLKIO
VDD/2
Item Clock low-level period Clock high-level period Clock cycle Cock I/O delay time
Pin CLKITV CLKIDTV CLKIPC CLKIO
Parameter tLO tHI tCK tOUT
min 7.5 7.5 15.0 5
max -- -- -- 10
Unit ns ns ns ns
(2) Output system clock timing
tHI tCK
XTAL tLO tOUT1
VDD/2
DCLK1
VDD/2
tD1
DCLK1B
VDD/2
tOUT2
tHI2
tCK2
DCLK2 tLO2 tD2
VDD/2
DCLK2B
VDD/2
Item Clock low-level period Clock high-level period Clock cycle DCLK1 delay time DCLK1B delay time Clock low-level period Clock high-level period Clock cycle DCLK2 delay time DCLK2B delay time
Pin
Parameter tLO
min 7.5 7.5 15.0 0 -1 15.0 15.0 30.0 0 -1
max -- -- -- 5 +1 -- -- -- 2 +1
Unit ns ns ns ns ns ns ns ns ns ns
XTAL
tHI tCK tOUT1 tD1 tLO2 tHI2 tCK2 tOUT2 tD2
DCLK1 DCLK1B
DCLK2
DCLK2 DCLK2B
No. 7023-13/14
LC74982W
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 2001. Specifications and information herein are subject to change without notice. PS No. 7023-14/14

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